I connect silicon, software, and the systems in between.
Turning complex engineering into things that just work.
Different disciplines. One connected system.
SELECT A DISCIPLINE TO EXPLORESELECTED EXPERIENCE
Built at the intersection of disciplines.
Designed to move engineering forward.
Front-end subsystem RTL for 8+ test chips. Bringing digital and analog IP together, with timing closure, lint, and clock domain crossing analysis to support design sign-off.
At Intel’s Central Engineering Group, I deliver front-end RTL collateral and integration flows for next-generation IPs. The work connects subsystem design with the analysis needed to enable silicon and design sign-off.
End-to-end EDA automation that catches methodology gaps early and makes engineering workflows more repeatable.
I architected subsystem integration flows and built Quality-of-Results metrics for timing, area, lint, and CDC health. I also led a GitHub migration across multiple test chip teams to standardize version control and streamline developer workflows.
Embedded firmware, C++ tooling, and interoperability testing. Connecting low-level engineering to real-world Wi-Fi reliability.
As a Software Validation & Automation Intern in Intel’s Client Computing Group, I led driver certification integration for Wi-Fi 6, Wi-Fi 6E, and PMF. I built tooling for test environment and device setup, and frameworks to validate drivers across network and vendor configurations.
THE PERSON BEHIND THE SYSTEMS
I’m Adin, an engineer based in Longview, Washington. My work lives where hardware and software come together: from embedded C++ to RTL integration and the automation that ties it all together.
I like understanding the whole system, finding the friction, and building a clearer path through it.
More about my backgroundB.S., Embedded Systems Engineering Technology
Oregon Institute of Technology · 2024
Seven years with Oregon VEX Robotics competitions. Training judges and evaluating 1,000+ student teams as a Judging Advisor.
Led weekly AI learning on methodology, token optimization, and model selection. Fluent in written Spanish, too.
MY TOOLKIT
Verilog · SystemVerilog · IP-XACT
Timing closure · Lint · CDC
C / C++ · Python · Tcl · Perl
Bash · Dart / Flutter · Linux / UNIX
Git / GitHub · CI/CD · Pytest
Flow development · EDA methodology
LET’S BUILD SOMETHING
Have a system to connect, a challenge to untangle,
or an idea worth exploring? Let’s talk.